A hard disk drive is a non-volatile storage device which stores digitally encoded data on one or more rapidly rotating platters with magnetic surfaces, collectively referred to as the disk. CML and CMOS technologies, when used in an integrated circuit such as a preamplifier integrated circuit in a disk drive system, require a conversion of CML differential voltage levels to CMOS compatible voltage levels. CML voltage levels represent the two values of a data bit (to be stored on the disk) typically by alternately setting one of the two voltage levels to be more positive than the other. A typical CML circuit operates with a differential swing of about two to three hundred millivolts (mV), although but smaller and larger swings are possible. Thus, a CML signal is more generally a differential digital logic signal. A typical CMOS circuit operates according to a single ended voltage, with two specified voltage ranges (respectively corresponding to a high-side data-path and a low-side data-path) that represent the two values of the data bit (to be stored on the disk).
With respect to a write driver, i.e., typically the circuit in a preamplifier that is responsible for controlling the data that is to be written on the disk via by the write head, write driver rise time and common mode (CM) are two parameters that can affect density and bit error rate in an integrated circuit design that embodies the write driver. In existing designs, there is always significant discrepancy in rise time and common mode between simulation and empirical data, due at least in part to inaccuracy of large signal simulation. Unfortunately, with existing approaches, a designer is not able to adjust the alignment of the high-side and low-side CMOS signals. Thus, the designer has to live with the alignment of the CMOS signals that is inherent with the silicon used to fabricate the integrated circuit design, even though the signals have been correctly simulated. Alternately, the designer may have to re-spin the parts to fix the alignment, which in turn affects cost and time to market.